About
I'm a PhD student at Harvard advised by David Brooks and Gu-Yeon Wei. I’m honored to be supported by the NSF Graduate Research Fellowship. My interests span heterogeneous and configurable accelerators, GPU systems, and networking for efficient AI workloads. I work across hardware and software to understand compute, memory, and communication costs in system performance and energy efficiency.
Previously, I studied computer science at UC Berkeley, worked in the SLICE Lab with John Wawrzynek and Krste Asanović, and received a SCALE Scholarship in 2024. I've interned on architecture at NVIDIA and CPU performance and GPU RTL design at Apple.
Publications
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From Chat to Agents on the Edge: A Cross-Framework Characterization of LLM Inference on Edge GPUs
IISWC 2026
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High-Throughput SAT Sampling
DATE 2025
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DEMOTIC: A Differentiable Sampler for Multi-Level Digital Circuits
ASP-DAC 2025
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Late Breaking Results: Differential and Massively Parallel Sampling of SAT Formulas
DAC 2024
Selected Work
PISTIL compiler and accelerator — Compiler support and attention optimizations for transformer models on a four-chiplet accelerator, alongside prototyping future chiplet designs.
GPU power for LLM inference — Characterizing power and performance across serving configurations, including prefill/decode disaggregation.
Saturn tapeout — Co-led a RISC-V vector processor tapeout on Intel 16nm.
uArchDB — Microarchitecture event logging and trace analysis for CPUs and accelerators in Chipyard.